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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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Low-Voltage 1:22 Differential PECL/HSTL Clock Driver
The MC100EP223 is a low skew 1-to-22 differential driver, designed with clock distribution in mind. It accepts two clock sources into an input multiplexer. The selected signal is fanned out to 22 identical differential outputs. * 200ps Part-to-Part Skew * 50ps Output-to-Output Skew * Differential Design * Open Emitter HSTL Compatible Outputs * 3.3V VCC * Both PECL and HSTL Inputs * 75k Input Pulldown Resistors * Thermally Enhanced 64 lead Exposed Pad LQFP The EP223 is specifically designed, modeled and produced with low skew as the key goal. Optimal design and layout serve to minimize gate-to-gate skew within a device, and empirical modeling is used to determine process control limits that ensure consistent tpd distributions from lot to lot. The net result is a dependable, guaranteed low skew device. The EP223 HSTL outputs are not realized in the conventional manner. To minimize part-to-part and output-to-output skew, the HSTL compatible output levels are generated with an open emitter architecture. The outputs are pulled down with 50 to ground, rather than the typical 50 to VDDQ pullup of a "standard" HSTL output. Because the HSTL outputs are pulled to ground, the EP223 does not utilize the VDDQ supply of the HSTL standard. The output levels are derived from VCC. In the case of an asynchronous control, there is a chance of generating a `runt' clock pulse when the device is enabled/disabled. To avoid this, the output enable (OE) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state.
MC100EP223
LOW-VOLTAGE 1:22 DIFFERENTIAL PECL/HSTL CLOCK DRIVER
TC SUFFIX 64-LEAD LQFP PACKAGE CASE 840K-01
To ensure that the tight skew specification is met it is necessary that both sides of the differential output are terminated into 50, even if only one side is being used. In most applications, all 22 differential pairs will be used and therefore terminated. In the case where fewer than 22 pairs are used, it is necessary to terminate at least the output pairs on the same package side as the pair(s) being used on that side, in order to maintain minimum skew. Failure to do this will result in small degradations of propagation delay (on the order of 10-20ps) of the output(s) being used which, while not being catastrophic to most designs, will mean a loss of skew margin.
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. 03/01
(c) Motorola, Inc. 2001
1
REV 2
MC100EP223
VCCO VCCO 33 32 31 30 29 28 27 26 25 VCCO Q14 Q14B Q15 Q15B Q16 Q16B Q17 Q17B Q18 Q18B Q19 Q19B Q20 Q20B VCCO 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VCCO Q10B Q12B Q13B 34 Q21 0 Q11B
Q7B
Q8B
Q9B
Q10
Q12
48 VCCO Q6B Q6 Q5B Q5 Q4B Q4 Q3B Q3 Q2B Q2 Q1B Q1 Q0B Q0 VCCO 49 50 51 52 53 54 55 56
47
46
45
44
43
42
41
40
39
38
37
36
MC100EP223
57 58 59 60 61 62 63 64
PECL_CLKB
HSTL_CLKB
PECL_CLK
HSTL_CLK
CLK_SEL
VCCO
VCCI
GND
NC
NC
NC
NC
Figure 1. 64-Lead Pinout (Top View) CLK_SEL PIN NAMES
Pins HSTL_CLK, HSTL_CLKB PECL_CLK, PECL_CLKB Q0:21, Q0B:21B CLK_SEL OE GND VCCI VCCO Function Differential HSTL Inputs Differential PECL Inputs Differential HSTL Outputs Active Clock Select Input Output Enable Ground Core VCC I/O VCC
HSTL_CLK HSTL_CLK
Q21B
OE
Q13 35
Q11
Q7
Q8
Q9
22
Q0 - Q21 Q0 - Q21
LVPECL_CLK LVPECL_CLK OE
1
22 LEN Q D
Figure 2. Logic Symbol SIGNAL GROUPS
FUNCTION
OE 0 0 1 1 CLK_SEL 0 1 0 1 Q0:21, Q0B:21B Q = Low, QB = High Q = Low, QB = High HSTL_CLK, HSTL_CLKB PECL_CLK, PECL_CLKB
Level HSTL HSTL LVPECL LVCMOS/LVTTL
Direction Input Output Input Input
Signal HSTL_CLK, HSTL_CLKB Q0:21, Q0B:21B PECL_CLK, PECL_CLKB CLK_SEL, OE
MOTOROLA
2
TIMING SOLUTIONS DL207 -- Rev 0
MC100EP223
HSTL DC CHARACTERISTICS
0C Symbol VOH VOL VIH VIL VX Characteristic Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Crossover Voltage VX+0.1 -0.3 0.68 Min Typ Max Min 1.0 0.4 1.6 VX-0.1 0.9 25C Typ Max Min 85C Typ Max Unit V V V V V
PECL DC CHARACTERISTICS
0C Symbol VIH VIL Characteristic Input HIGH Voltage (Note 1.) Input LOW Voltage (Note 1.) Min 2.135 1.490 Typ Max 2.420 1.825 Min 2.135 1.490 25C Typ Max 2.420 1.825 150 Min 2.135 1.490 85C Typ Max 2.420 1.825 150 Unit V V A
IIH Input HIGH Current 150 1. These values are for VCC = 3.3V. Level specifications vary 1:1 with VCC.
AC CHARACTERISTICS (VEE = GND, VCC =VCC(min) to VCC(max))
0C Symbol tPLH, tPHL tskew fmax VPP VCMR tr, tf Characteristic Propagation Delay to Output IN (Differential) Within-Device Skew Part-to-Part Skew (Diff) Maximum Input Frequency Minimum Input Swing PECL_CLK Common Mode Range PECL_CLK Output Rise/Fall Time (20-80%) 300 600 300 600 300 600 600 Min Typ 1.0 50 200 250 600 Max Min 25C Typ 1.0 50 200 250 600 Max Min 85C Typ 1.0 50 200 250 ps MHz mV V ps Max Unit ns
Power Supply Characteristics
Symbol VCCI VCCO Core VCC I/O VCC Characteristic Min 3.0 1.6 Typ 3.3 1.8 Max 3.6 2.0 Unit V V
ICC IEE
Power Supply Current Power Supply Current
mA mA
TIMING SOLUTIONS DL207 -- Rev 0
3
MOTOROLA
MC100EP223
APPLICATIONS INFORMATION
Using the thermally enhanced package of the MC100EP223 The MC100EP223 uses a thermally enhanced 64 lead LQFP package. This package provides the low thermal impedance that supports the power consumption of the MC100EP223 high-speed bipolar integrated circuit and eases the power management task for the system design. An exposed pad at the bottom of the package establishes thermal conductivity from the package to the printed circuit board. In order to take advantage of the enhanced thermal capabilitites of this package, it is recommended to solder the exposed pad of the package to the printed circuit board. The attachment process for exposed pad package is the same as for any standard surface mount package. Vias are recommended from the pad on the board down to an appropriate plane in the board that is capable of distributing the heat. In order to supply enough solder paste to fill those vias and not starve the solder joints, it may be required to stencil print solder paste onto the printed circuit pad. This pad should match the dimensions of the exposed pad. The dimensions of the exposed pad are shown on the package outline in this specification. For thermal system analysis and junction temperature calculation the thermal resistance parameters of the package is provided: Thermal Resistance
Convection LFPM Natural 100 200 400 800 a. b. c. d. RTHJAa C/W 57.1 50.0 46.9 43.4 38.6 RTHJAb C/W 24.9 21.3 20.0 18.7 16.9 15.8 9.7 RTHJCc C/W RTHJBd C/W
Junction to ambient, single layer test board, per JESD51-6 Junction to ambient, four conductor layer test board (2S2P), per JES51-6 Junction to case, per MIL-SPEC 883E, method 1012.1 Junction to board, four conductor layer test board (2S2P) per JESD 51-8
It is recommended that users employ thermal modeling analysis to assist in applying the general recommendations to their particular application. The exposed pad of the MC100EP223 package does not have an electrical low impedance path to the substrate of the integrated circuit and its terminals.
MOTOROLA
4
TIMING SOLUTIONS DL207 -- Rev 0
MC100EP223
OUTLINE DIMENSIONS
TC SUFFIX PLASTIC LQFP PACKAGE, EXPOSED PAD CASE 840K-01 ISSUE O
4X 4X 16 TIPS
0.2 H A-B D D
PIN 1 IDENTIFIER 1 64 49 48
0.2 C A-B D
A2 0.05
S
(S) Z1 Z R 0.25
GAGE PLANE
A
B E1 E A1 R1 L (L1)
3X
VIEW Y
16 17 32 33
E1/2
VIEW AA E/2
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M-1994. 3. DATUMS A, B AND D TO BE DETERMINED AT DATUM PLANE H. 4. DIMENSIONS D AND E TO BE DETERMINED AT SEATING PLANE C. 5. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE THAN 0.08 mm. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07 mm. 6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 mm PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 mm AND 0.25 mm FROM THE LEAD TIP. DIM A A1 A2 b b1 c c1 D D1 e E E1 L L1 R1 R2 S F G Z Z1 Z2 Z3 MILLIMETERS MIN MAX --- 1.60 0.05 0.15 1.35 1.45 0.17 0.27 0.17 0.23 0.09 0.20 0.09 0.16 12.00 BSC 10.00 BSC 0.50 BSC 12.00 BSC 10.00 BSC 0.45 0.75 1.00 REF 0.08 --- 0.08 --- 0.20 --- 6.00 7.00 6.00 7.00 0_ 7_ 0_ --- 11 _ 13 _ 11 _ 13 _
D1/2 D/2 D1 D H A
4X
Z2 0.08 C
J C
SEATING PLANE
64X
b
4X
Z3 VIEW AA
J
0.08
M
C A-B D X
X=A, B OR D
C L AB AB
BASE METAL
e/2
60X
e
F
VIEW Y
8 b1
8
c
PLATING
ROTATED 90 _ CLOCKWISE
SECTION AB-AB
TIMING SOLUTIONS DL207 -- Rev 0
CCCC EEEE CCCC EEEE CCCC EEEE
8 b
c1 8
G
EXPOSED PAD
VIEW J-J
5
MOTOROLA
MC100EP223
NOTES
MOTOROLA
6
TIMING SOLUTIONS DL207 -- Rev 0
MC100EP223
NOTES
TIMING SOLUTIONS DL207 -- Rev 0
7
MOTOROLA
MC100EP223
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MOTOROLA
8
TIMING SOLUTIONS MC100EP223/D DL207 -- Rev 0

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